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1-1TMS320DM643xDMPBlockDiagram..................................................................................12
2-1TMS320C64x+MegamoduleBlockDiagram...........................................................................17
2-2C64x+CacheMemoryArchitecture......................................................................................19
4-1OverallClockingDiagram.................................................................................................31
4-2VPBE/DACClocking.......................................................................................................35
5-1PLL1StructureintheTMS320DM643xDMP..........................................................................39
5-2PLL2StructureintheTMS320DM643xDMP..........................................................................43
5-3PeripheralIDRegister(PID)..............................................................................................49
5-4ResetTypeStatusRegister(RSTYPE).................................................................................49
5-5PLLControlRegister(PLLCTL)..........................................................................................50
5-6PLLMultiplierControlRegister(PLLM).................................................................................51
5-7PLLControllerDivider1Register(PLLDIV1)...........................................................................51
5-8PLLControllerDivider2Register(PLLDIV2)..........................................................................52
5-9PLLControllerDivider3Register(PLLDIV3)..........................................................................52
5-10OscillatorDivider1Register(OSCDIV1)................................................................................53
5-11BypassDividerRegister(BPDIV)........................................................................................54
5-12PLLControllerCommandRegister(PLLCMD).........................................................................55
5-13PLLControllerStatusRegister(PLLSTAT).............................................................................55
5-14PLLControllerClockAlignControlRegister(ALNCTL)...............................................................56
5-15PLLDIVRatioChangeStatusRegister(DCHANGE)..................................................................57
5-16ClockEnableControlRegister(CKEN).................................................................................58
5-17ClockStatusRegister(CKSTAT)........................................................................................59
5-18SYSCLKStatusRegister(SYSTAT).....................................................................................60
6-1PowerandSleepController(PSC)Integration.........................................................................62
6-2PeripheralRevisionandClassInformationRegister(PID)...........................................................69
6-3InterruptEvaluationRegister(INTEVAL)................................................................................69
6-4ModuleErrorPendingRegister1(MERRPR1)........................................................................70
6-5ModuleErrorClearRegister1(MERRCR1)............................................................................70
6-6PowerDomainTransitionCommandRegister(PTCMD).............................................................71
6-7PowerDomainTransitionStatusRegister(PTSTAT).................................................................71
6-8PowerDomainStatus0Register(PDSTAT0)..........................................................................72
6-9PowerDomainControl0Register(PDCTL0)..........................................................................73
6-10ModuleStatusnRegister(MDSTATn)..................................................................................74
6-11ModuleControlnRegister(MDCTLn)...................................................................................75
6ListofFiguresSPRU978E–March2008
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