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5.1PLLModule
5.2PLL1Control
PLLModule
TheDM643xDMPhastwoPLLs(PLL1andPLL2)thatprovideclockstodifferentpartsofthesystem.
PLL1providesclocks(thoughvariousdividers)tomostofthecomponentsoftheDM643xDMP.PLL2is
dedicatedtotheDDR2portandcomponentsforthevideoprocessingsubsystem(VPSS).Thetypical
referenceclockisthe27MHZcrystalinput,asmentionedinChapter4.
ThePLLcontrollerprovidesthefollowing:
•Glitch-FreeTransitions(onchangingclocksettings)
•DomainClocksAlignment
•ClockGating
•PLLpowerdown
Thevariousclockoutputsgivenbythecontrollerareasfollows:
•DomainClocks:SYSCLK[1:n]
•AuxiliaryClockfromreferenceclocksource:AUXCLK
•BypassDomainclock:SYSCLKBP
•ObserveClock:OBSCLK
VariousdividersthatcanbeusedontheDM643xDMPareasfollows:
•PLLControllerDividers(forSYSCLK[1:n]):PLLDIV1,...,PLLDIVn
•BypassDivider(forSYSCLKBP):BPDIV
•OscillatorDivider(forOBSCLK):OSCDIV1
Variousothercontrolssupportedareasfollows:
•PLLMultiplierControl:PLLM
•Software-programmablePLLBypass:PLLEN
PLL1suppliestheprimaryDM643xDMPsystemclock.SoftwarecontrolsthePLL1operationthroughthe
systemPLLcontroller1(PLLC1)registers.TheregistersusedinPLLC1arelistedinSection5.4.
Figure5-1showsthecustomizationofPLL1intheDM643xDMP.Thedomainclocksaredistributedtothe
coreclockdomains(discussedinSection4.2.1)andtherestofthedeviceasfollows:
•SYSCLK1:CLKDIV1Domain
•SYSCLK2:CLKDIV3Domain
•SYSCLK3:CLKDIV6Domain
•AUXCLK:CLKINDomain
•OBSCLK:CLKOUT0pin
•SYSCLKBP:VPBEinternalclocksource
ThePLL1multiplieriscontrolledbythePLLMbitofthePLLmultipliercontrolregister(PLLM).ThePLL1
outputclockmaybedivided-downforslowerdeviceoperationusingthePLLC1SYSCLKdividers
PLLDIV1,PLLDIV2,andPLLDIV3.
YouareresponsibletoadheretothePLLC1frequencyrangesandmultiplier/dividerratiosspecifiedinthe
datamanual.SeealsoSection4.2.1andSection4.2.2.
Atpower-up,PLL1ispowered-downanddisabled,andmustbepowered-upbysoftwarethroughthePLL1
PLLPWRDNbitinthePLLcontrolregister(PLLCTL).Bydefault,thesystemoperatesinbypassmodeand
thesystemclockisprovideddirectlyfromtheinputreferenceclock(MXI/CLKINpin).OncethePLLis
powered-upandlocked,softwarecanswitchthedevicetoPLLmodeoperationbysettingthePLLENbitin
PLLCTLto1.Ifthebootmodeofthedeviceissettofastboot(FASTBOOT=1),thebootloadercodein
theBootROMwillfollowthepreviousprocesstopower-upandlockthePLL,andswitchthedevicetoPLL
modetospeedupthebootprocess.Therefore,comingoutofafastboot,thedeviceisoperatinginPLL
mode.
38PLLControllerSPRU978E–March2008
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