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4.2.4I/ODomains
ClockDomains
TheI/Odomainsrefertothefrequenciesoftheperipheralsthatcommunicatethroughdevicepins.In
manycases,therearefrequencyrequirementsforaperipheralpininterfacethataresetbyanoutside
standardandmustbemet.Itisnotnecessarilypossibletoobtainthesefrequenciesfromtheon-chipclock
generationcircuitry,sothefrequenciesmustbeobtainedfromexternalsourcesandareasynchronousto
thecorefrequencydomainbydefinition.
Table4-5listsperipheralswithexternalI/Ointerface,andtheirI/Odomainclock/frequency.Italsoshows
thecoreclockdomainasareferencetoshowthecoreclockusedforinternalcommunications.See
sectionSection4.2.1formoredetailsoncoreclockdomains.Seedevice-specificdatamanualforthe
exactI/Oclockfrequencysupportedonthedevice.
Table4-5.PeripheralI/ODomainClock
I/O(External)DomainClockSourceOptions
I/ODomainClock
PeripheralFrequencyInternalClockSourceExternalClockSourceCoreClockDomain
DDR2125-166MHZPLLC2SYSCLK1—CLKDIV3
VPFE10-98MHZ—PCLKCLKDIV3
VPBE6.25-75MHZPLLC1SYSCLKBPVPBECLKCLKDIV3
(typically27MHZ)
PLLC2SYSCLK2PCLK
(typically54MHZ)
PCI33MHZ—PCICLKCLKDIV3
EMAC25MHZ—MTXCLK,MRXCLKCLKDIV6
VLYNQupto80MHZPLLC1SYSCLK3VLYNQ_CLOCKCLKDIV6
McBSPupto40MHZPLLC1SYSCLK3CLKS,CLKX,CLKRCLKDIV6
McASPupto40MHZPLLC1SYSCLK3AHCLKX,AHCLKR,CLKDIV6
ACLKX,ACLKR
GPIONA(asynchronous——CLKDIV6
interface)
EMIFANA(asynchronous——CLKDIV6
interface)
HPINA(asynchronous——CLKDIV6
interface)
I2Cupto400kHzMXI/CLKINSCLCLKIN
(typically27MHZ)
Timeroutputupto1/2CLKINMXI/CLKINTINP0L(Timer0),CLKIN
frequency(typically27MHZ)TINP1L(Timer1)
inputupto1/4CLKIN
frequency
WatchdogTimerNAMXI/CLKIN—CLKIN
(typically27MHZ)
PWMNA——CLKIN
UARTNA——CLKIN
HECCNA——CLKIN
34DeviceClockingSPRU978E–March2008
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