Filter
Top Products
www.ti.com
2.3MemoryControllers
2.3.1L1PController
MemoryControllers
TheC64x+Megamoduleimplementsatwo-levelinternalcache-basedmemoryarchitecturewithexternal
memorysupport.Level1memoryissplitintoseparateprogrammemory(L1Pmemory)anddatamemory
(L1Dmemory).Figure2-2showsadiagramofthememoryarchitecture.L1PandL1Dareconfigurableas
partL1RAM(normaladdressableon-chipmemory)andpartL1cache.L1memoryisaccessibletothe
CPUwithoutstalls.Level2memory(L2)canalsobesplitintoL2RAM(normaladdressableon-chip
memory)andL2cacheforcachingexternalmemorylocations.
ThefollowingcontrollersmanageRAM/cacheconfigurationandcachedatapaths:
•L1Pcontroller
•L1Dcontroller
•L2controller
•Externalmemorycontroller(EMC)
Theinternaldirectmemoryaccess(IDMA)controllermanagesDMAamongtheL1P,L1D,andL2
memories.
ThissectionbrieflydescribesthecacheandDMAcontrollers.Fordetailedinformationabouteachofthese
controllers,seetheTMS320C64x+DSPCacheUser’sGuide(SPRU862)andtheTMS320C64x+DSP
MegamoduleReferenceGuide(SPRU871).
Note:TheC64x+Megamoduleincludesthememorycontrollers;however,thephysicalL1P,L1D,
andL2memoriesarenotpartofthemegamodule,eventhoughtheyresideintheDSP
subsystem.Thus,thephysicalmemoriesaredescribedseparatelybecausetheC64x+
Megamodulesupportsavarietyofmemoryconfigurations.RefertoSection3.1formore
informationontheL1P,L1D,andL2memoryconfigurationspecifictotheDM643xDMP.
TheL1Pcontrolleristhehardwareinterfacebetweenlevel1programmemory(L1Pmemory)andthe
othercomponentsintheC64x+Megamodule(forexample,C64x+CPU,L2controller,andEMC).The
L1PcontrollerrespondstoinstructionfetchrequestsfromtheC64x+CPUandmanagestransfer
operationsbetweenL1PmemoryandtheL2controllerandbetweenL1PmemoryandtheEMC.
Refertothedevice-specificdatamanualfortheamountofL1Pmemoryonthedevice.TheL1Pcontroller
hasaregisterinterfacethatallowsyoutoconfigurepartoralloftheL1PRAMasnormalRAMoras
cache.Youcanconfigurecachesizesof0KB,4KB,8KB,16KB,or32KBoftheRAM.
TheL1Pisdividedintotworegions—denotedL1Pregion0andL1Pregion1.ThisistheL1Parchitecture
ontheDM643xDMP:
•L1Pregion0:Notpopulatedwithmemory.
•L1Pregion1:Populatedwithmemorythatcanbeconfiguredasmappedmemoryorcache.TheL1P
region1memoryhas0waitstate.Thisregionisshownas“L1PRAM/Cache”inthedevice-specific
datamanual.
TheDM643xDMPdoesnotsupporttheL1Pmemoryprotectionfeatureofthestandard
C64x+Megamodule.
RefertotheTMS320C64x+DSPCacheUser’sGuide(SPRU862)andtotheL1Pcontrollersectionofthe
TMS320C64x+DSPMegamoduleReferenceGuide(SPRU871)formoreinformationontheL1Pcontroller
andforadescriptionofitscontrolregisters.
18TMS320C64x+MegamoduleSPRU978E–March2008
SubmitDocumentationFeedback