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5.4.14ClockEnableControlRegister(CKEN)
PLLControllerRegisters
Theclockenablecontrolregister(CKEN)isshowninFigure5-16anddescribedinTable5-18.CKEN
providesclockenablecontrolformiscellaneousoutputclocks.CKENisonlyapplicabletoPLLC1,not
PLLC2.
Figure5-16.ClockEnableControlRegister(CKEN)
3116
Reserved
R-0
15210
ReservedOBSENAUXEN
R-0R/W-1R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-18.ClockEnableControlRegister(CKEN)FieldDescriptions
BitFieldValueDescription
31-2Reserved0Reserved
1OBSENOBSCLKenable.ActualOBSCLKstatusisshownintheclockstatusregister(CKSTAT).
0OBSCLKisdisabled.
1OBSCLKisenabled.ForOBSCLKtotoggle,boththeOBSENbitandtheOD1ENbitintheoscillator
divider1register(OSCDIV1)mustbesetto1.
0AUXENAUXCLKenable.ActualAUXCLKstatusisshownintheclockstatusregister(CKSTAT).
0AUXCLKisdisabled.
1AUXCLKisenabled.
58PLLControllerSPRU978E–March2008
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