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5.4.4PLLMultiplierControlRegister(PLLM)
5.4.5PLLControllerDivider1Register(PLLDIV1)
PLLControllerRegisters
ThePLLmultipliercontrolregister(PLLM)isshowninFigure5-6anddescribedinTable5-8.
Figure5-6.PLLMultiplierControlRegister(PLLM)
3116
Reserved
R-0
15540
ReservedPLLM
R-0R/W-10hor13h
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLC1,PLLMdefaultsto10h(PLL1multiplyby17);forPLLC2,PLLMdefaultsto13h(PLL2multiplyby20).
Table5-8.PLLMultiplierControlRegister(PLLM)FieldDescriptions
BitFieldValueDescription
31-5Reserved0Reserved
4-0PLLM0-1FhPLLmultiplierselect.Multipliervalue=PLLM+1.Forexample,PLLM=16(10h)meansmultiplyby17.
Seedevice-specificdatamanualforvalidmultipliervaluesforeachPLL.
ThePLLcontrollerdivider1register(PLLDIV1)isshowninFigure5-7anddescribedinTable5-9.Divider
1controlsdividerforSYSCLK1.
Figure5-7.PLLControllerDivider1Register(PLLDIV1)
3116
Reserved
R-0
1514540
D1ENReservedRATIO
R/W-0R-0R/W-0or1
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLC1,RATIOdefaultsto0(PLL1divideby1);forPLLC2,RATIOdefaultsto1(PLL2divideby2).
Table5-9.PLLControllerDivider1Register(PLLDIV1)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D1ENDivider1enable.
0Divider1isdisabled.
1Divider1isenabled.
14-5Reserved0Reserved
4-0RATIO0-1FhDividerratio.Dividervalue=RATIO+1.Forexample,RATIO=0meansdivideby1.
SPRU978E–March2008PLLController51
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