Filter
Top Products
www.ti.com
C64x+ CPU
Fetch Path Data Path
Write
Buffer
L1D
Cache
L1D
SRAM
L1 Data
L1P
Cache
L1P
SRAM
L1 Program
L2 Cache
L2 SRAM
L2 Unified Data/Program Memory
External Memory
64 bit
256 bit
128 bit
256 bit
256 bit
2 x 64 bit
Legend:
addressable memory
cache memory
data paths managed by
cache controller
256 bit
MemoryControllers
Figure2-2.C64x+CacheMemoryArchitecture
SPRU978E–March2008TMS320C64x+Megamodule19
SubmitDocumentationFeedback