Filter
Top Products
www.ti.com
6.2PowerDomainandModuleTopology
PowerDomainandModuleTopology
TheDM643xDMPincludesonepowerdomain--theAlwaysOnpowerdomain.TheAlwaysOnpower
domainisalwaysonwhenthechipison.TheAlwaysOndomainispoweredbytheV
DD
pinsofthe
DM643xDMP(seethedevice-specificdatamanual).AlloftheDM643xDMPmodulesresidewithinthe
AlwaysOnpowerdomain.Table6-1listsallthepossibleperipheralsontheDM643xDMP,theirLPSC
assignments,anddefaultmodulestates.Refertothedevice-specificdatamanualfortheperipherals
availableonagivendevice.ThemodulestatesaredefinedinSection6.3.2.
Table6-1.DM643xDMPDefaultModuleConfiguration
LPSC
NumberModuleNameDefaultModuleState(MDSTAT.STATE)
0VPSS(master)SwRstDisable
1VPSS(slave)SwRstDisable
2EDMACCSwRstDisable
3EDMATC0SwRstDisable
4EDMATC1SwRstDisable
5EDMATC2SwRstDisable
6EMACMemoryControllerSwRstDisable
7MDIOSwRstDisable
8EMACSwRstDisable
9McASP0SwRstDisable
10Reserved-
11VLYNQSwRstDisable
12HPISwRstDisable
13DDR2MemoryControllerSwRstDisable
14EMIFASwRstDisable,ifconfigurationpinsAEM[2:0]=000b
Enable,ifconfigurationpinsAEM[2:0]=others
15PCISwRstDisable
16McBSP0SwRstDisable
17McBSP1SwRstDisable
18I2CSwRstDisable
19UART0SwRstDisable
20UART1SwRstDisable
21ReservedSwRstDisable
(1)
22HECCSwRstDisable
23PWM0SwRstDisable
24PWM1SwRstDisable
25PWM2SwRstDisable
26GPIOSwRstDisable
27TIMER0SwRstDisable
28TIMER1SwRstDisable
29-38Reserved-
39C64x+CPUEnable
40Reserved-
(1)
Forthisreserveddomain,itisimportantnottosetthecorrespondingSTATEbitsinthemodule
statusnregisters(MDSTAT0-MDSTAT39)todisable.FormoredetailsonMDSTATnandthe
STATEbits,seeSection6.7.9.
SPRU978E–March2008PowerandSleepController63
SubmitDocumentationFeedback