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88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 26 Document Classification: Proprietary Information December 2, 2008, Preliminary
1.2.4 PCI Express Interface Pin Assignments
Table 6: PCI Express Interface Pin Assignments
Pin Name I/O Pin
Type
Power
Rail
Description
PEX_CLK_P/N I/O HCSL PEX_AVDD PCI Express Reference Clock
100 MHz, differential
This clock can be configured as input or output according to the
reset strap (see Table 32, Reset Configuration, on page 67).
NOTE: For Output mode, 50-ohm, pull-down resistors are
required.
PEX_TX_P/N O CML PEX_AVDD Transmit Lane
Differential pair of PCI Express transmit data
PEX_RX_P/N I CML PEX_AVDD Receive Lane
Differential pair of PCI Express receive data
PEX_ISET I Analog Current reference. Pull down to VSS through a 5 k
Ω resistor.
See the 88F6180, 88F6190, 88F6192, and 88F6281 Design
Guide for the recommended resistor value.