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88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 4 Document Classification: Proprietary Information December 2, 2008, Preliminary
FEATURES
The 88F6281 includes:
• High-performance CPU core, running at up to
1.5 GHz, with integrated, four-way, set-associative
L1 16-KB I-cache/16-KB D-cache and unified,
256-KB, four-way, set-associative L2 cache
• High-bandwidth dual-port DDR2 memory interface
(16-bit DDR2 SDRAM @ up to 800 MHz data rate)
• PCI Express (x1) port with integrated PHY
• Two Gigabit Ethernet (10/100/1000 Mbps) MACs
• USB 2.0 port with integrated PHY
• Two SATA 2.0 ports with integrated 3 Gbps SATA II
PHY
• Security Cryptographic engine
• S/PDIF (Sony/Philips Digital Interconnect Format) /
I
2
S (Integrated Interchip Sound) Audio in/out
interface
• SD/SDIO/MMC interface
• TDM SLIC/SLAC Codec interface
• Two XOR engines, each containing two XOR/DMA
channels (a total of four XOR/DMA channels)
• MPEG Transport Stream (TS) interface
• SPI port with SPI flash boot support
• 8-bit NAND flash interface with boot support
• Two 16550 compatible UART interfaces
• TWSI port
• 50 multi-purpose pins
• Internal Real Time Clock (RTC)
• Interrupt controller
• Timers
• 128-bit eFuse (one-time programmable memory)
Sheeva
™
CPU core
• Up to 1.5 GHz
• 32-bit and 16-bit RISC architecture
• Compliant with v5TE architecture, as published in
the ARM Architect Reference Manual, Second
Edition
• Includes MMU to support virtual memory features
• 256-KB, four-way, set-associative L2 unified cache
• 16-KB, four-way, set-associative I-cache
• 16-KB, four-way, set-associative D-cache
• 64-bit internal data bus
• Branch Prediction Unit
• Supports JTAG/ARM ICE
• Supports both Big and Little Endian modes
DDR2 SDRAM controller
• 16-bit interface
• Up to 400 MHz clock frequency (800 MHz data
rate)
• DDR SDRAM with a clock ratio of 1:N and 2:N
between the DDR SDRAM and the CPU core,
respectively
• SSTL 1.8V I/Os
• Auto calibration of I/Os output impedance
• Supports four DRAM chip selects
• Supports all DDR devices densities up to 2 Gb
• Supports up to 32 open pages (page per bank)
• Up to 2 GB total address space
• Supports on-board DDR designs (no DIMM
support)
• Supports 2T mode, to enable high-frequency
operation under heavy load configuration
• Supports DRAM bank interleaving
• Supports up to a 128-byte burst per single memory
access
PCI Express interface (x1)
• PCI Express Base 1.1 compatible
• Integrated low-power SERDES PHY, based on
proven Marvell
®
SERDES technology
• Serves as a Root Complex or an Endpoint port
• x1 link width
• 2.5 Gbps data rate
• Lane polarity reversal support
• Maximum payload size of 128 bytes
• Single Virtual Channel (VC-0)
• Replay buffer support
• Extended PCI Express configuration space
• Advanced Error Reporting (AER) support
• Power management: L0s and software L1 support
• Interrupt emulation message support
• Error message support
PCI Express master specific features
• Single outstanding read transaction
• Maximum read request of up to 128 bytes
• Maximum write request of up to 128 bytes
• Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
• Supports up to eight read request transactions
• Maximum read request size of 4 KB
• Maximum write request of 128 bytes
• Supports PCI Express access to all of the
controller’s internal registers
Two Integrated GbE (10/100/1000) MAC ports
• Supports 10/100/1000 Mbps
• Dedicated DMA for data movement between
memory and port