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88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 72 Document Classification: Proprietary Information December 2, 2008, Preliminary
Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts
executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according
to sample at reset setting, see Table 32, Reset Configuration, on page 67.
For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281
Functional Specifications.
As part of the CPU boot code, the CPU typically performs the following:
Configures the PCI Express address map.
Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization
(sets <InitEn> bit [0] to 1 in the SDRAM Initialization Control register).
Sets the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.