Filter
Top Products
88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 58 Document Classification: Proprietary Information December 2, 2008, Preliminary
MPP_34 /
GE1[14]
NA MII1_TXEN (out) NA NA
MPP_35 /
GE1[15]
NA MII1_RXERR (in) NA NA
Table 27: Ethernet Ports Pins Multiplexing (Continued)
Pin Name 1xGMII RGMII0+MII1/
MMII1
2xRGMII MII0/MMII0+
RGMII1
Note
When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals
(except those marked as NA) must be implemented. For example, if using MII, and the
chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35])
must still be configured accordingly and must have a pull-down resistor.