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88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 74 Document Classification: Proprietary Information December 2, 2008, Preliminary
7.3 Bypass Register
The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR
holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI
input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0
when the TAP FSM is in the Capture-DR state.
7.4 JTAG Scan Chain
The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during
the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to
sequentially access all of the data pins both for driving and strobing data. For further details, refer to
the BSDL Description file for the device.
7.5 ID Register
The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device
information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID
register is shown in Table 34, which describes the various ID Code fields.
Table 34: IDCODE Register Map
Bits Value Description
31:28 0x0 Version (4'b0010 for version A0, 4'b0011 for A1, etc.)
27:12 0x6281 Part number
11:1 0x1AB Manufacturer ID
0 1 Mandatory