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Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 40 Document Classification: Proprietary Information December 2, 2008, Preliminary
1.2.15 Audio (S/PDIF / I
2
S) Interface
Note
All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin
Multiplexing, on page 51).
If the Audio interface is not used, leave all of the signals unconnected.
The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin
multiplexing option.
Table 17: Audio (S/PDIF / I
2
S) Interface Signal Assignment
Pin Name I/O Pin
Type
Power
Rail
Description
AU_SPDIFI I CMOS VDDO/
VDD_GE_B
S/PDIF In
AU_SPDIFO O CMOS VDDO/
VDD_GE_B
S/PDIF Out
AU_
SPDFRMCLK
O CMOS VDDO/
VDD_GE_B
S/PDIF Recovered Master Clock (256 x F
s
)
1
For the frequency of this clock, see the Audio External
Reference Clock section of Table 45, Reference Clock AC
Timing Specifications, on page 86.
AU_I2SBCLK O CMOS VDDO/
VDD_GE_B
I
2
S Bit Clock (64 x F
s
)
AU_I2SDO O CMOS VDDO/
VDD_GE_B
Transmitter Data Out
AU_I2SLRCLK O CMOS VDDO/
VDD_GE_B
I
2
S Left/Right Clock (1 x F
s
)
AU_I2SMCLK O CMOS VDDO/
VDD_GE_B
I
2
S Master Clock (256 x F
s
)
AU_I2SDI I CMOS VDDO/
VDD_GE_B
I
2
S Receiver Data In
AU_EXTCLK I CMOS VDDO/
VDD_GE_B
External Audio Clock
For the frequency of this clock, see the Audio External
Reference Clock section of Table 45, Reference Clock AC
Timing Specifications, on page 86.
1. F
s
is the audio sample rate.