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Appendix D Register-Level Programming
PC-LPM-16/PnP User Manual D-28
National Instruments Corporation
Analog Input Circuitry Programming Sequence
1. Initiate an A/D conversion.
A low to high transition on OUT0 or on EXTCONV* initiates A/D
conversion. Clear the CALEN bit in Command Register 2 to enable
counter 0 and the EXTCONV*.
When an A/D conversion is initiated, the ADC stores the result in
the A/D FIFO at the end of its conversion cycle. If EXTCONV*
initiates the conversion, OUT0 must be set high.
2. Read the A/D conversion result.
Read the A/D FIFO Register to get the A/D conversion results.
Before you read the A/D FIFO, however, you must read the Status
Register to determine whether the A/D FIFO contains any results.
To read the A/D conversion results, complete the following steps:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Low-Byte
Register first, then read the A/D FIFO High-Byte Register to
get the result. The first reading returns the low byte of 16-bit
data, and the second reading returns the high byte.
Reading the Low and High-Byte A/D FIFO Registers removes the A/D
conversion result from the A/D FIFO.
The DAVAIL bit indicates whether one or more A/D conversion results
are stored in the A/D FIFO. If the DAVAIL bit is cleared, the A/D FIFO
is empty and reading the A/D FIFO Register returns meaningless data.
When an A/D conversion is initiated, the DAVAIL bit should be set
after 20 µs. If you use EXTCONV* for A/D timing, the DAVAIL bit
should be set 20 µs after a rising edge in EXTCONV*.
An A/D FIFO overflow condition occurs if you initiate more than
256 conversions and store them in the A/D FIFO before reading the A/D
FIFO Register. If this condition occurs, the OVERFLOW bit is set in
the Status Register 2 to indicate that one or more A/D conversion
results have been lost because of FIFO overflow. Write to the A/D Clear
Register to reset this error flag.
a.Book : l.Appendix D Page 28 Wednesday, November 20, 1996 6:36 PM