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Appendix D Register-Level Programming
PC-LPM-16/PnP User Manual D-32
National Instruments Corporation
during the programming. Write 0 to the A/D Clear Register to
empty the FIFO (8-bit write), then read the low and high bytes from
the A/D FIFO (PC-LPM-16 only).
4. Start and service the data acquisition operation.
To start the data acquisition operation, write the most significant
byte of the sample interval to the Counter 0 Data Register. This
enables counter 0 to start counting.
When the data acquisition operation starts, service the operation by
reading the A/D FIFO Register every time an A/D conversion result
becomes available. Perform the following sequence until you have
read the desired number of conversion results:
a. Read the Status Register (8-bit read).
b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to
get the result.
You can also use interrupts to service the data acquisition operation.
This topic is discussed in the A/D Interrupt Programming section later
in this appendix.
An overflow error condition may occur during a data acquisition
operation. This error condition is reported through the Status Register,
and the overflow should be checked every time the Status Register is
read.
An overflow condition occurs if more than 256 A/D conversions have
been stored in the A/D FIFO since the A/D FIFO was last read; that is,
the A/D FIFO is full and cannot accept any more data. This condition
occurs if the software loop reading the A/D FIFO Register is not fast
enough to keep up with the A/D conversion rate. When an overflow
occurs, at least one A/D conversion result is lost. An overflow condition
has occurred if the OVERFLOW bit in the Status Register is set.
Clear the OVERFLOW bit in the Status Register by writing to the A/D
Clear Register.
To stop the A/D conversion sequence, write 34 to the Counter 0 Mode
Register. This stops the generation of pulses on OUT0.
a.Book : l.Appendix D Page 32 Wednesday, November 20, 1996 6:36 PM