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2.1.2ClockConfiguration
2.1.3DDR2MemoryControllerInternalClockDomains
2.2MemoryMap
PeripheralArchitecture
ThefrequencyofPLL2_SYSCLK1isconfiguredbyselectingtheappropriatePLLmultiplieranddivider
ratio.ThePLLmultiplieranddividerratioareselectedbyprogrammingregisterswithinPLLC2.Table1
showsalistofPLLmultiplieranddividersettingstoachievecertainDDR2frequencies.Thedatain
Table1isderivedbyassuminga27-MHZreferenceclock.Seethedevice-specificdatamanualforthe
clockfrequenciesthataresupported.SeetheTMS320DM643xDMPDSPSubsystemReferenceGuide
(SPRU978)forinformationonthePLLcontroller.
Note:PLLC2shouldbeconfiguredandastableclockpresentonPLL2_SYSCLK1beforereleasing
theDDR2memorycontrollerfromreset.
Table1.PLLC2Configuration
PLLMultiplierPLLFrequency(MHZ)DividerRatioX2_CLKFrequency(MHZ)DDR2ClockFrequency(MHZ)
287563252126
195132256.6128.3
297833261130.5
205402270135
318373279139.5
215672283.5141.8
328643288144
225942297148.5
236212310155.3
246482324162
256752337.5168.8
TherearetwoclockdomainswithintheDDR2memorycontroller.Thetwoclockdomainsaredrivenby
VCLKandadivided-downby2versionofX2_CLKcalledMCLK.ThecommandFIFO,writeFIFO,and
readFIFOdescribedinSection2.8areallontheVCLKdomain.Fromthis,youcanseethatVCLKdrives
theinterfacetotheperipheralbus.
TheMCLKdomainconsistsoftheDDR2memorycontrollerstatemachineandmemory-mappedregisters.
ThisclockdomainisclockedattherateoftheexternalDDR2memory,X2_CLK/2.
ToconservepowerwithintheDDR2memorycontroller,VCLK,MCLK,andX2_CLKmaybestopped.See
Section2.16forproperclockstopprocedures.
Seethedevice-specificdatamanualforinformationdescribingthedevicememory-map.
DDR2MemoryController 10SPRU986B–November2007
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