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3.2.4ConfiguringDDRPHYControlRegister(DDRPHYCR)
4DDR2MemoryControllerRegisters
DDR2MemoryControllerRegisters
TheDDRPHYcontrolregister(DDRPHYCR)containsareadlatency(READLAT)fieldthathelpsthe
DDR2memorycontrollerdeterminewhentosamplereaddata.TheREADLATfieldshouldbe
programmedtoavalueequaltoCASlatencyplusroundtripboarddelayminus1.Theminimum
READLATvalueisCASlatencyplus1andthemaximumREADLATvalueisCASlatencyplus3(again,
theREADLATfieldwouldbeprogrammedtothesevaluesminus1).
Whencalculatingroundtripboarddelaythesignalsofprimaryconcernarethedifferentialclocksignals
(DDR_CLKandDDR_CLK)anddatastrobesignals(DDR_DQS).Forthesesignals,calculatetheround
tripboarddelayfromtheDDR2memorycontrollertothememoryandthenchoosethemaximumdelayto
determinetheREADLATvalue.Inthisexamplewewillassumetheroundtripboarddelayis1DDR_CLK
cycle,thereforeREADLATcanbecalculatedasfollows:
READLAT=CASlatency+roundtripboarddelay–1=4+1–1=4
Table21.DDRPHYControlRegister(DDRPHYCR)Configuration
RegisterFieldNameDescriptionRegisterValue
DLLRESETProgrammedtoremovetheDDR2memorycontrollerDLLfrom0
reset.
DLLPWRDNProgrammedtopoweruptheDDR2memorycontrollerDLL.0
READLATReadlatencyisequaltoCASlatencyplusroundtripboarddelay4
fordataminus1.
Table22,Table23,andTable24listthememory-mappedregistersrelatedtotheDDR2memory
controller.Seethedevice-specificdatamanualforthememoryaddressesoftheseregisters.
TheDDR2memorycontrollerperipheralinterfacestotheCPUusinga64-bitdatabusandoperatesin
little-endianmode(seeSection2.6formoreinformationregardingendiannessconsiderations).
TheDDR2memorycontrollermemory-mappedregistersare32-bitregisters,andwhenaccessingthem
viathe64-bitinterface,two32-bitregistersareaccessedineachcycle.Therefore,forexample,when
accessingtheSDRAMbankconfigurationregister(SDBCR)andtheSDRAMrefreshcontrolregister
(SDRCR),thefollowingdataisobtained:
D63-32D31-0
SDRAMrefreshcontrolregister(SDRCR)SDRAMbankconfigurationregister(SDBCR)
DDR2MemoryController 40SPRU986B–November2007
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