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4.8InterruptMaskedRegister(IMR)
DDR2MemoryControllerRegisters
Theinterruptmaskedregister(IMR)displaysthestatusoftheinterruptwhenitisenabled.Iftheinterrupt
conditionoccursandthecorrespondingbitintheinterruptmasksetregister(IMSR)isset,thentheIMR
bitisset.TheIMRbitisnotsetiftheinterruptisnotenabledinIMSR.TheIMRisshowninFigure26and
describedinTable32.
Figure26.InterruptMaskedRegister(IMR)
3116
Reserved
R-0
153210
ReservedLTMReserved
R-0R/W1C-0R-0
LEGEND:R/W=Read/Write;R=Readonly;W1C=Write1toclear(writing0hasnoeffect);-n=valueafterreset
Table32.InterruptMaskedRegister(IMR)FieldDescriptions
BitFieldValueDescription
31-3Reserved0Reserved
2LTMLinetrapmasked.Writea1toclearLTMandtheLTbitintheinterruptrawregister(IRR);awriteof0
hasnoeffect.
0Alinetrapconditionhasnotoccurred.
1Illegalmemoryaccesstype(onlysetiftheLTMSETbitinIMSRisset).SeeSection2.14formore
details.
1-0Reserved0Reserved
SPRU986B–November2007DDR2MemoryController49
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