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4.1SDRAMStatusRegister(SDRSTAT)
DDR2MemoryControllerRegisters
Table22.DDR2MemoryControllerRegistersRelativetoBaseAddress20000000h
OffsetAcronymRegisterDescriptionSection
4hSDRSTATSDRAMStatusRegisterSection4.1
8hSDBCRSDRAMBankConfigurationRegisterSection4.2
ChSDRCRSDRAMRefreshControlRegisterSection4.3
10hSDTIMRSDRAMTimingRegisterSection4.4
14hSDTIMR2SDRAMTimingRegister2Section4.5
20hPBBPRPeripheralBusBurstPriorityRegisterSection4.6
C0hIRRInterruptRawRegisterSection4.7
C4hIMRInterruptMaskedRegisterSection4.8
C8hIMSRInterruptMaskSetRegisterSection4.9
CChIMCRInterruptMaskClearRegisterSection4.10
E4hDDRPHYCRDDRPHYControlRegisterSection4.11
F0hVTPIOCRVTPIOControlRegisterSection4.12
Table23.DDR2MemoryControllerRegistersRelativetoBaseAddress01C42000h
OffsetAcronymRegisterDescriptionSection
38hDDRVTPRDDRVTPRegisterSection4.13
Table24.DDR2MemoryControllerRegistersRelativetoBaseAddress01C40000h
OffsetAcronymRegisterDescriptionSection
4ChDDRVTPERDDRVTPEnableRegisterSection4.14
TheSDRAMstatusregister(SDRSTAT)isshowninFigure19anddescribedinTable25.
Figure19.SDRAMStatusRegister(SDRSTAT)
3116
Reserved
R-4000h
153210
ReservedPHYRDYReserved
R-0R-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-x=valueisindeterminateafterreset
Table25.SDRAMStatusRegister(SDRSTAT)FieldDescriptions
BitFieldValueDescription
31-3Reserved0Reserved
2PHYRDYDDR2memorycontrollerDLLready.ReflectswhethertheDDR2memorycontrollerDLLispoweredup
andlocked.
0DLLisnotready,eitherpowereddown,inreset,ornotlocked.
1DLLispoweredup,locked,andreadyforoperation.
1-0Reserved0Reserved
SPRU986B–November2007DDR2MemoryController41
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