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1PLLC2Configuration.......................................................................................................10
2DDR2MemoryControllerSignalDescriptions.........................................................................11
3DDR2SDRAMCommands...............................................................................................12
4TruthTableforDDR2SDRAMCommands............................................................................12
5AddressableMemoryRanges............................................................................................20
616-BitExternalMemory...................................................................................................21
732-BitExternalMemory...................................................................................................21
8BankConfigurationRegisterFieldsforAddressMapping............................................................22
9LogicalAddress-to-DDR2SDRAMAddressMapfor32-BitSDRAM...............................................23
10LogicalAddress-to-DDR2SDRAMAddressMapfor16-bitSDRAM................................................23
11DDR2MemoryControllerFIFODescription............................................................................26
12RefreshUrgencyLevels...................................................................................................29
13ResetSources..............................................................................................................30
14DDR2SDRAMConfigurationbyMRSCommand.....................................................................32
15DDR2SDRAMConfigurationbyEMRS(1)Command................................................................32
16SDRAMBankConfigurationRegister(SDBCR)Configuration......................................................38
17DDR2MemoryRefreshSpecification...................................................................................38
18SDRAMRefreshControlRegister(SDRCR)Configuration..........................................................38
19SDRAMTimingRegister(SDTIMR)Configuration....................................................................39
20SDRAMTimingRegister2(SDTIMR2)Configuration.................................................................39
21DDRPHYControlRegister(DDRPHYCR)Configuration............................................................40
22DDR2MemoryControllerRegistersRelativetoBaseAddress20000000h.......................................41
23DDR2MemoryControllerRegistersRelativetoBaseAddress01C42000h......................................41
24DDR2MemoryControllerRegistersRelativetoBaseAddress01C40000h......................................41
25SDRAMStatusRegister(SDRSTAT)FieldDescriptions.............................................................41
26SDRAMBankConfigurationRegister(SDBCR)FieldDescriptions.................................................42
27SDRAMRefreshControlRegister(SDRCR)FieldDescriptions.....................................................44
28SDRAMTimingRegister(SDTIMR)FieldDescriptions...............................................................45
29SDRAMTimingRegister2(SDTIMR2)FieldDescriptions...........................................................46
30PeripheralBusBurstPriorityRegister(PBBPR)FieldDescriptions.................................................47
31InterruptRawRegister(IRR)FieldDescriptions.......................................................................48
32InterruptMaskedRegister(IMR)FieldDescriptions...................................................................49
33InterruptMaskSetRegister(IMSR)FieldDescriptions...............................................................50
34InterruptMaskClearRegister(IMCR)FieldDescriptions.............................................................51
35DDRPHYControlRegister(DDRPHYCR)FieldDescriptions.......................................................52
36VTPIOControlRegister(VTPIOCR)FieldDescriptions..............................................................53
37DDRVTPRegister(DDRVTPR)FieldDescriptions...................................................................54
38DDRVTPEnableRegister(DDRVTPER)FieldDescriptions........................................................54
A-1DocumentRevisionHistory...............................................................................................55
SPRU986B–November2007ListofTables5
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