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2.8.1CommandOrderingandScheduling,AdvancedConcept
PeripheralArchitecture
TheDDR2memorycontrollerperformscommandre-orderingandschedulinginanattempttoachieve
efficienttransferswithmaximumthroughput.Thegoalistomaximizetheutilizationofthedata,address,
andcommandbuseswhilehidingtheoverheadofopeningandclosingDDR2SDRAMrows.Command
re-orderingtakesplacewithinthecommandFIFO.
Typically,agivenmasterissuescommandsonasinglepriority.EDMAtransfercontrollerreadandwrite
portsaredifferentmasters.TheDDR2memorycontrollerfirstreorderscommandsfromeachmaster
basedonthefollowingrules:
•Selectstheoldestcommand(firstcommandinthequeue)
•Selectsareadbeforeawriteif:
–Thereadistoadifferentblockaddress(2048bytes)thanthewrite
–Thereadhasgreaterorequalpriority
Thesecondbulletabovemaybeviewedasanexceptiontothefirstbullet.Thismeansthatforan
individualmaster,allofitscommandswillcompletefromoldesttonewest,withtheexceptionthataread
maybeadvancedaheadofanolder,lowerorequalprioritywrite.Followingthisscheduling,eachmaster
mayhaveonecommandreadyforexecution.
Next,theDDR2memorycontrollerexamineseachofthecommandsselectedbytheindividualmasters
andperformsthefollowingreordering:
•Amongallpendingreads,selectsreadstorowsalreadyopen.Amongallpendingwrites,selectswrites
torowsalreadyopen.
•Selectsthehighestprioritycommandfrompendingreadsandwritestoopenrows.Ifmultiple
commandshavethehighestpriority,thentheDDR2memorycontrollerselectstheoldestcommand.
TheDDR2memorycontrollermaynowhaveafinalreadandwritecommand.IftheReadFIFOisnotfull,
thenthereadcommandwillbeperformedbeforethewritecommand,otherwisethewritecommandwillbe
performedfirst.
Besidescommandsreceivedfromon-chipresources,theDDR2memorycontrolleralsoissuesrefresh
commands.TheDDR2memorycontrollerattemptstodelayrefreshcommandsaslongaspossibleto
maximizeperformancewhilemeetingtheSDRAMrefreshrequirements.AstheDDR2memorycontroller
issuesread,write,andrefreshcommandstoDDR2SDRAMmemory,itadherestothefollowingrules:
1.RefreshrequestresultingfromtheRefreshMustlevelofurgencybeingreached
2.Readrequestwithoutahigherprioritywrite(selectedfromabovereorderingalgorithm)
3.RefreshrequestresultingfromtheRefreshNeedlevelofurgencybeingreached
4.Writerequest(selectedfromabovereorderingalgorithm)
5.RefreshrequestresultingfromRefreshMaylevelofurgencybeingreached
6.Requesttoenterself-refreshmode
Thefollowingresultsfromtheaboveschedulingalgorithm:
•Allwritesfromasinglemasterwillcompleteinorder
•Allreadsfromasinglemasterwillcompleteinorder
•Fromthesamemaster,anyreadtothesamelocation(orwithin2048bytes)asapreviouswritewill
completeinorder
SPRU986B–November2007DDR2MemoryController27
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