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1.3FunctionalBlockDiagram
SCR
DDR2
memory
controller
BUS BUS
External
DDR2 SDRAM
DSP
Master
peripherals
EDMA
VPSS
1.4SupportedUseCaseStatement
1.5IndustryStandard(s)ComplianceStatement
Introduction
TheDDR2memorycontrolleristhemaininterfacetoexternalDDR2memory.Figure1displaysthe
generaldatapathstoon-chipperipheralsandexternalDDR2SDRAM.
Masterperipherals,EDMA,theARMprocessor,andDSPcanaccesstheDDR2memorycontroller
throughtheswitchedcentralresource(SCR).
Figure1.DataPathstoDDR2MemoryController
TheDDR2memorycontrollersupportsJESD79D-2ADDR2-400SDRAMmemoriesutilizingeither32-bit
or16-bitoftheDDR2memorycontrollerdatabus.SeeSection3formoredetails.
TheDDR2memorycontrolleriscompliantwiththeJESD79D-2ADDR2SDRAMstandardwiththe
exceptionofthefollowingfeaturelist:
•OnDieTermination(ODT).TheDDR2memorycontrollerdoesnotincludeanyon-dieterminating
resistors.Furthermore,theon-dieterminatingresistorsoftheDDR2SDRAMdevicemustbedisabled
bytyingtheODTinputpinoftheDDR2SDRAMtoground.
•DifferentialDQS.TheDDR2memorycontrollersupportssingleendedDQSsignals.
DDR2MemoryController 8SPRU986B–November2007
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