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ListofFigures
1DataPathstoDDR2MemoryController..................................................................................8
2DDR2MemoryControllerClockBlockDiagram.........................................................................9
3DDR2MemoryControllerSignals........................................................................................11
4RefreshCommand.........................................................................................................13
5DCABCommand...........................................................................................................14
6DEACCommand...........................................................................................................15
7ACTVCommand...........................................................................................................16
8DDR2READCommand...................................................................................................17
9DDR2WRTCommand....................................................................................................18
10DDR2MRSandEMRSCommand......................................................................................19
11ByteAlignment..............................................................................................................20
12LogicalAddress-to-DDR2SDRAMAddressMap......................................................................24
13DDR2SDRAMColumn,Row,andBankAccess......................................................................25
14DDR2MemoryControllerFIFOBlockDiagram........................................................................26
15DDR2MemoryControllerResetBlockDiagram.......................................................................30
16DDR2MemoryControllerPowerSleepControllerDiagram..........................................................34
17ConnectingDDR2MemoryControllerfor32-BitConnection.........................................................37
18ConnectingDDR2MemoryControllerfor16-BitConnection.........................................................37
19SDRAMStatusRegister(SDRSTAT)....................................................................................41
20SDRAMBankConfigurationRegister(SDBCR).......................................................................42
21SDRAMRefreshControlRegister(SDRCR)...........................................................................44
22SDRAMTimingRegister(SDTIMR).....................................................................................45
23SDRAMTimingRegister2(SDTIMR2)..................................................................................46
24PeripheralBusBurstPriorityRegister(PBBPR).......................................................................47
25InterruptRawRegister(IRR).............................................................................................48
26InterruptMaskedRegister(IMR).........................................................................................49
27InterruptMaskSetRegister(IMSR).....................................................................................50
28InterruptMaskClearRegister(IMCR)...................................................................................51
29DDRPHYControlRegister(DDRPHYCR).............................................................................52
30VTPIOControlRegister(VTPIOCR)....................................................................................53
31DDRVTPRegister(DDRVTPR).........................................................................................54
32DDRVTPEnableRegister(DDRVTPER)..............................................................................54
4ListofFiguresSPRU986B–November2007
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