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2.7AddressMapping
PeripheralArchitecture
TheDDR2memorycontrollerviewsexternalDDR2SDRAMasonecontinuousblockofmemory.This
statementistrueregardlessofthenumberofexternalphysicaldevicesmappedtoagivenchipselect
space.TheDDR2memorycontrollerreceivesDDR2memoryaccessrequestsalongwitha32-bitlogical
addressfromtherestofthesystem.Inturn,theDDR2memorycontrollerusesthelogicaladdressto
generatearow/page,column,andbankaddressfortheDDR2SDRAM.Thenumberofcolumnandbank
addressbitsusedisdeterminedbytheIBANKandPAGESIZEfieldsintheSDRAMbankconfiguration
register(SDBCR)(seeTable8).
Table8.BankConfigurationRegisterFieldsforAddressMapping
BitFieldBitValueBitDescription
IBANKDefinesthenumberofinternalbanksontheexternalDDR2memory.
01bank
1h2banks
2h4banks
3h8banks
PAGESIZEDefinesthepagesizeofeachpageoftheexternalDDR2memory.
0256words(requires8columnaddressbits)
1h512words(requires9columnaddressbits)
2h1024words(requires10columnaddressbits)
3h2048words(requires11columnaddressbits)
AsstatedinTable8,theIBANKandPAGESIZEfieldsofSDBCRcontrolthemappingofthelogical,
sourceaddressoftheDDR2memorycontrollertotheDDR2SDRAMrow,column,andbankaddressbits.
TheDDR2memorycontrollerlogicaladdressalwayscontains13rowaddressbits,whereasthenumberof
columnandbankbitsaredeterminedbytheIBANKandPAGESIZEfields.Table9andTable10show
howthelogicaladdressbitsmaptotheDDR2SDRAMrow,column,andbankbitsforcombinationsof
IBANKandPAGESIZEvalues.ThesameDDR2memorycontrollerpinsprovidetherowandcolumn
addresstotheDDR2SDRAM,thustheDDR2memorycontrollerappropriatelyshiftstheaddressduring
rowandcolumnaddressselection.
Figure12showshowthisaddress-mappingschemeorganizestheDDR2SDRAMrows,columns,and
banksintothedevicememorymap.Notethatduringalinearaccess,theDDR2memorycontroller
incrementsthecolumnaddressasthelogicaladdressincrements.WhentheDDR2memorycontroller
reachesapage/rowboundary,itmovesontothesamepage/rowinthenextbank.Thismovement
continuesuntilthesamepagehasbeenaccessedinallbanks.TotheDDR2SDRAM,thisprocesslooks
asshowninFigure13.
Bytraversingacrossbankswhileremainingonthesamerow/page,theDDR2memorycontroller
maximizesthenumberofactivatedbanksforalinearaccess.Thisresultsinthemaximumnumberof
openpageswhenperformingalinearaccessbeingequaltothenumberofbanks.NotethattheDDR2
memorycontrollerneveropensmorethanonepageperbank.
EndingthecurrentaccessisnotaconditionthatforcestheactiveDDR2SDRAMrowtobeclosed.The
DDR2memorycontrollerleavestheactiverowopenuntilitbecomesnecessarytocloseit.Thisdecreases
thedeactivate-reactivateoverhead.
22DDR2MemoryControllerSPRU986B–November2007
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