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2.6EndiannessConsiderations
PeripheralArchitecture
TheDDR2memorycontrollersupportslittle-endianoperatingmode.Thisdeterminestheorderinwhich
dataontheinternaldatabusiswrittentoorreadfromdevicesthatarenotaswideastheinternaldata
bus.However,theDDR2memorycontrollermaintainsthenaturalorderofendianoperations.Thatis,a
streamofdatastartingatanyaddressNwillalwaysbeaccessedinthecorrectorincrementingdata
order.TheDDR2memorycontrollerwillalwaysaccessaddressNpriortoN+1inanydatawidth.Table6
andTable7showoperationoftheDDR2memorycontrollerforboth16-bitand32-bitexternalmemory.
Seethedevice-specificdatamanualforthememorywidthsthataresupported.
Table6.16-BitExternalMemory
InternalData(64-BitDDR_A[2:1]DDR_D[15:0]
0123456789ABCDEFh00CDEFh
0123456789ABCDEFh0189ABh
0123456789ABCDEFh104567h
0123456789ABCDEFh110123h
Table7.32-BitExternalMemory
InternalData(64-Bit)DDR_A[2]DDR_D[31:0]
0123456789ABCDEFh089ABCDEFh
0123456789ABCDEFh101234567h
SPRU986B–November2007DDR2MemoryController21
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