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2.4.2Deactivation(DCABandDEAC)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DCAB
DDR_A[10]
DDR_CAS
DDR_CLK
PeripheralArchitecture
Theprechargeallbankscommand(DCAB)isperformedafteraresettotheDDR2memorycontrolleror
followingtheinitializationsequence.DDR2SDRAMsalsorequirethiscyclepriortoarefresh(REFR)and
modesetregistercommands(MRSandEMRS).DuringaDCABcommand,DDR_A[10]isdrivenhighto
ensurethedeactivationofallbanks.Figure5showsthetimingdiagramforaDCABcommand.
Figure5.DCABCommand
14DDR2MemoryControllerSPRU986B–November2007
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