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3SupportedUseCases
3.1ConnectingtheDDR2MemoryControllertoDDR2Memory
3.2ConfiguringMemory-MappedRegisterstoMeetDDR2-400Specification
SupportedUseCases
TheDDR2memorycontrollerallowsahighdegreeofprogrammabilityforshapingDDR2accesses.The
programmabilityinherenttotheDDR2memorycontrollerprovidestheDDR2memorycontrollerwiththe
flexibilitytointerfacewithavarietyofDDR2devices.ByprogrammingtheSDRAMbankconfiguration
register(SDBCR),SDRAMrefreshcontrolregister(SDRCR),SDRAMtimingregister(SDTIMR),and
SDRAMtimingregister2(SDTIMR2),theDDR2memorycontrollercanbeconfiguredtomeetthedata
sheetspecificationforJESD79D-2AcompliantDDR2SDRAM.
ThissectionpresentsanexampledescribinghowtointerfacetheDDR2memorycontrollertoaJESD79D
DDR2-4001-Gbdevice.TheDDR2memorycontrollerisassumedtobeoperatingat133MHZ.
ThefollowingfiguresshowhowtoconnecttheDDR2memorycontrollertoaDDR2device.Figure17
displaysa32-bitinterface;therefore,two16-bitDDR2devicesareconnectedtotheDDR2memory
controller.FromFigure17,youcanseethatthedatabus,datastrobe,anddatamask(byteenable)
signalsarepoint-to-pointwhereasallotheraddress,control,andclocksarenot.Figure18displaysa
16-bitinterface;therefore,allsignalsarepoint-to-point.Seethedevice-specificdatamanualforthedata
buswidthsthataresupported.
Aspreviouslystated,fourmemory-mappedregistersmustbeprogrammedtoconfiguretheDDR2memory
controllertomeetthedatasheetspecificationoftheattachedDDR2device.Theregistersare:
•SDRAMbankconfigurationregister(SDBCR)
•SDRAMrefreshcontrolregister(SDRCR)
•SDRAMtimingregister(SDTIMR)
•SDRAMtimingregister2(SDTIMR2)
Inadditiontotheseregisters,theDDRPHYcontrolregister(DDRPHYCR)mustalsobeprogrammed.The
configurationofDDRPHYCRisnotdependentontheDDR2devicespecificationbutratherontheboard
layout.
Thefollowingsectionsdescribehowtoconfigureeachoftheseregisters.SeeSection4formore
informationontheDDR2memorycontrollerregisters.
36DDR2MemoryControllerSPRU986B–November2007
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