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4.10InterruptMaskClearRegister(IMCR)
DDR2MemoryControllerRegisters
Theinterruptmaskclearregister(IMCR)disablestheDDR2memorycontrollerinterrupt.Onceaninterrupt
isenabled,itmaybedisabledbywritinga1totheIMCRbit.TheIMCRisshowninFigure28and
describedinTable34.
Note:IftheLTMCLRbitinIMCRissetconcurrentlywiththeLTMSETbitintheinterruptmaskset
register(IMSR),theinterruptisnotenabledandneitherbitissetto1.
Figure28.InterruptMaskClearRegister(IMCR)
3116
Reserved
R-0
153210
ReservedLTMCLRReserved
R-0R/W1C-0R-0
LEGEND:R/W=Read/Write;R=Readonly;W1C=Write1toclear(writing0hasnoeffect);-n=valueafterreset
Table34.InterruptMaskClearRegister(IMCR)FieldDescriptions
BitFieldValueDescription
31-3Reserved0Reserved
2LTMCLRLinetrapinterruptclear.Writea1toclearLTMCLRandtheLTMSETbitintheinterruptmaskset
register(IMSR);awriteof0hasnoeffect.
0Linetrapinterruptisnotenabled.
1Linetrapinterruptisenabled;awriteof1totheLTMSETbitinIMSRoccurred.
1-0Reserved0Reserved
SPRU986B–November2007DDR2MemoryController51
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