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4.7InterruptRawRegister(IRR)
DDR2MemoryControllerRegisters
Theinterruptrawregister(IRR)displaystherawstatusoftheinterrupt.Iftheinterruptconditionoccurs,
thecorrespondingbitinIRRissetindependentofwhetherornottheinterruptisenabled.TheIRRis
showninFigure25anddescribedinTable31.
Figure25.InterruptRawRegister(IRR)
3116
Reserved
R-0
153210
ReservedLTReserved
R-0R/W1C-0R-0
LEGEND:R/W=Read/Write;R=Readonly;W1C=Write1toclear(writing0hasnoeffect);-n=valueafterreset
Table31.InterruptRawRegister(IRR)FieldDescriptions
BitFieldValueDescription
31-3Reserved0Reserved
2LTLinetrap.Writea1toclearLTandtheLTMbitintheinterruptmaskedregister(IMR);awriteof0has
noeffect.
0Alinetrapconditionhasnotoccurred.
1Illegalmemoryaccesstype.SeeSection2.14formoredetails.
1-0Reserved0Reserved
48DDR2MemoryControllerSPRU986B–November2007
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