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2.9RefreshScheduling
2.10Self-RefreshMode
PeripheralArchitecture
TheDDR2memorycontrollerissuesautorefresh(REFR)commandstoDDR2SDRAMdevicesatarate
definedintherefreshrate(RR)bitfieldintheSDRAMrefreshcontrolregister(SDRCR).Arefreshinterval
counterisloadedwiththevalueoftheRRbitfieldanddecrementsby1eachcycleuntilitreacheszero.
Oncetheintervalcounterreacheszero,itreloadswiththevalueoftheRRbit.Eachtimetheinterval
counterexpires,arefreshbacklogcounterincrementsby1.Conversely,eachtimetheDDR2memory
controllerperformsaREFRcommand,thebacklogcounterdecrementsby1.Thismeanstherefresh
backlogcounterrecordsthenumberofREFRcommandstheDDR2memorycontrollercurrentlyhas
outstanding.
TheDDR2memorycontrollerissuesREFRcommandsbasedonthelevelofurgency.Thelevelof
urgencyisdefinedinTable12.Whenevertherefreshlevelofurgencyisreached,theDDR2memory
controllerissuesaREFRcommandbeforeservicinganynewmemoryaccessrequests.FollowingaREFR
command,theDDR2memorycontrollerwaitsT_RFCcycles,definedintheSDRAMtimingregister
(SDTIMR),beforerecheckingtherefreshurgencylevel.
Inadditiontotherefreshcounterpreviouslymentioned,aseparatebacklogcounterensurestheinterval
betweentwoREFRcommandsdoesnotexceed8×therefreshrate.Thisbacklogcounterincrementsby1
eachtimetheintervalcounterexpiresandresetstozerowhentheDDR2memorycontrollerissuesa
REFRcommand.Whenthisbacklogcounterisgreaterthan7,theDDR2memorycontrollerissuesfour
REFRcommandsbeforeservicinganynewmemoryrequests.
TherefreshcountersdonotoperatewhentheDDR2memoryisinself-refreshmode.
Table12.RefreshUrgencyLevels
UrgencyLevelDescription
RefreshMayBacklogcountisgreaterthan0.IndicatesthereisabacklogofREFRcommands,whentheDDR2memory
controllerisnotbusyitwillissuetheREFRcommand.
RefreshReleaseBacklogcountisgreaterthan3.IndicatesthelevelatwhichenoughREFRcommandshavebeenperformed
andtheDDR2memorycontrollermayservicenewmemoryaccessrequests.
RefreshNeedBacklogcountisgreaterthan7.IndicatestheDDR2memorycontrollershouldraisetheprioritylevelofa
REFRcommandaboveservicinganewmemoryaccess.
RefreshMustBacklogcountisgreaterthan11.IndicatesthelevelatwhichtheDDR2memorycontrollershouldperforma
REFRcommandbeforeservicingnewmemoryaccessrequests.
Settingtheselfrefresh(SR)bitintheSDRAMrefreshcontrolregister(SDRCR)to1forcestheDDR2
memorycontrollertoplacetheexternalDDR2SDRAMinalow-powermode(selfrefresh),inwhichthe
DDR2SDRAMmaintainsvaliddatawhileconsumingaminimalamountofpower.WhentheSRbitis
asserted,theDDR2memorycontrollercontinuesnormaloperationuntilalloutstandingmemoryaccess
requestshavebeenservicedandtherefreshbackloghasbeencleared.Atthispoint,allopenpagesof
DDR2SDRAMareclosedandaself-refresh(SLFRFR)command(anautorefreshcommandwith
DDR_CKElow)isissued.
TheDDR2memorycontrollerexitstheself-refreshstatewhenamemoryaccessisreceivedorwhenthe
SRbitinSDRCRisclearedto0.Whileintheself-refreshstate,ifarequestforamemoryaccessis
received,theDDR2memorycontrollerservicesthememoryaccessrequest,returningtotheself-refresh
stateuponcompletion.TheDDR2memorycontrollerwillnotwakeupfromtheself-refreshstate(whether
fromamemoryaccessrequestorfromclearingtheSRbit)untilT_CKE+1cycleshaveexpiredsincethe
self-refreshcommandwasissued.ThevalueofT_CKEisdefinedintheSDRAMtiming2register
(SDTIMR2).
Afterexitingfromtheself-refreshstate,theDDR2memorycontrollerwillnotimmediatelystartexecuting
commands.Instead,itwillwaitT_SXNR+1clockcyclesbeforeissuingnon-readcommandsand
T_SXRD+1clockcyclesbeforeissuingreadcommands.TheSDRAMtiming2register(SDTIM2)
programsthevaluesofT_SXNRandT_SXRD.
SPRU986B–November2007DDR2MemoryController29
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