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Table9.LogicalAddress-to-DDR2SDRAMAddressMapfor32-BitSDRAM
SDBCRBitLogicalAddress
(1)
IBANKPAGESIZE31302928272625242322:161514131211109:21:0
00-nrb=13ncb=8
10-nrb=13nbb=1ncb=8
2h0-nrb=13nbb=2ncb=8
3h0-nrb=13nbb=3ncb=8
01-nrb=13ncb=9
11-nrb=13nbb=1ncb=9
2h1-nrb=13nbb=2ncb=9
3h1-nrb=13nbb=3ncb=9
02h-nrb=13ncb=10
12h-nrb=13nbb=1ncb=10
2h2h-nrb=13nbb=2ncb=10
3h2h-nrb=13nbb=3ncb=10
03h-nrb=13ncb=11
13h-nrb=13nbb=1ncb=11
2h3h-nrb=13nbb=2ncb=11
3h3hnrb=13nbb=3ncb=11
(1)
Legend:ncb=numberofcolumnaddressbits;nrb=numberofrowaddressbits;nbb=numberofbankaddressbits.
Table10.LogicalAddress-to-DDR2SDRAMAddressMapfor16-bitSDRAM
SDBCRBitLogicalAddress
(1)
IBANKPAGESIZE3130292827262524232221:15141312111098:10
00-nrb=13ncb=8
10-nrb=13nbb=1ncb=8
2h0-nrb=13nbb=2ncb=8
3h0-nrb=13nbb=3ncb=8
01-nrb=13ncb=9
11-nrb=13nbb=1ncb=9
2h1-nrb=13nbb=2ncb=9
3h1-nrb=13nbb=3ncb=9
02h-nrb=13ncb=10
12h-nrb=13nbb=1ncb=10
2h2h-nrb=13nbb=2ncb=10
3h2h-nrb=13nbb=3ncb=10
03h-nrb=13ncb=11
13h-nrb=13nbb=1ncb=11
2h3h-nrb=13nbb=2ncb=11
3h3h-nrb=13nbb=3ncb=11
(1)
Legend:ncb=numberofcolumnaddressbits;nrb=numberofrowaddressbits;nbb=numberofbankaddressbits.
SPRU986B–November2007DDR2MemoryController23
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