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2.8.2CommandStarvation
2.8.3PossibleRaceCondition
PeripheralArchitecture
Thereorderingandschedulingruleslistedabovemayleadtocommandstarvation,whichisthe
preventionofcertaincommandsfrombeingprocessedbytheDDR2memorycontroller.Command
starvationresultsfromthefollowingconditions:
•Acontinuousstreamofhigh-priorityreadcommandscanblockalow-prioritywritecommand
•AcontinuousstreamofDDR2SDRAMcommandstoarowinanopenbankcanblockcommandsto
theclosedrowinthesamebank.
Toavoidtheseconditions,theDDR2memorycontrollercanmomentarilyraisethepriorityoftheoldest
commandinthecommandFIFOafterasetnumberoftransfershavebeenmade.ThePR_OLD_COUNT
bitfieldintheperipheralbusburstpriorityregister(PBBPR)setsthenumberofthetransfersthatmustbe
madebeforetheDDR2memorycontrollerwillraisethepriorityoftheoldestcommand.
Note:LeavingthePR_OLD_COUNTbitsattheirdefaultvalue(FFh)disablesthisfeatureofthe
EMIF.ThismeanscommandscanstayinthecommandFIFOindefinitely.Therefore,these
bitsshouldbesettoFEhimmediatelyfollowingresettoenablethisfeaturewiththehighest
levelofallowablememorytransfers.Itissuggestedthatsystemlevelprioritizationbesetto
avoidplacinghigh-bandwidthmastersonthehighestprioritylevels.Thesebitscanbeleftas
FEhunlessadvancedbandwidth/prioritizationcontrolisrequired.
AraceconditionmayexistwhencertainmasterswritedatatotheDDR2memorycontroller.Forexample,
ifmasterApassesasoftwaremessageviaabufferinDDR2memoryanddoesnotwaitforindicationthat
thewritecompletes,whenmasterBattemptstoreadthesoftwaremessageitmayreadstaledataand
thereforereceiveanincorrectmessage.InordertoconfirmthatawritefrommasterAhaslandedbeforea
readfrommasterBisperformed,masterAmustwaitforthewritecompletionstatusfromtheDDR2
memorycontrollerbeforeindicatingtomasterBthatthedataisreadytoberead.IfmasterAdoesnot
waitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround:
1.Performtherequiredwrite.
2.PerformadummywritetotheDDR2memorycontrollerSDRAMStatusregister.
3.PerformadummyreadtotheDDR2memorycontrollerSDRAMStatusregister.
4.IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The
completionofthereadinstep3ensuresthatthepreviouswritewasdone.
TheEDMAandATAperipheralsdonotneedtoimplementtheaboveworkaround.Ifaperipheralisnot
listedhere,thentheaboveworkaroundisrequired.Refertothedevice-specificdatamanualformore
information.
DDR2MemoryController 28SPRU986B–November2007
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