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3.2.3ConfiguringSDRAMTimingRegisters(SDTIMRandSDTIMR2)
SupportedUseCases
TheSDRAMtimingregister(SDTIMR)andSDRAMtimingregister2(SDTIMR2)configuretheDDR2
memorycontrollertomeetthedatasheettimingparametersoftheattachedDDR2device.Eachfieldin
SDTIMRandSDTIMR2correspondstoatimingparameterintheDDR2datasheetspecification.Table19
andTable20displaytheregisterfieldnameandcorrespondingDDR2datasheetparameternamealong
withthedatasheetvalue.Thesetablesalsoprovideaformulatocalculatetheregisterfieldvalueand
displaystheresultingcalculation.Eachoftheequationsincludeaminus1becausetheregisterfieldsare
definedintermsofDDR2clockcyclesminus1.SeeSection4.4andSection4.5formoreinformation.
Table19.SDRAMTimingRegister(SDTIMR)Configuration
DDR2Data
RegisterFieldManualDataManualFormulaRegister
NameParameterNameDescriptionValue(nS)(Registerfieldmustbe≥)Value
T_RFCt
RFC
Refreshcycletime127.5(t
RFC
×f
DDR2_CLK
)-116
T_RPt
RP
Prechargecommandto20(t
RP
×f
DDR2_CLK
)-12
refreshoractivate
command
T_RCDt
RCD
Activatecommandto20(t
RCD
×f
DDR2_CLK
)-12
read/writecommand
T_WRt
WR
Writerecoverytime15(t
WR
×f
DDR2_CLK
)-11
T_RASt
RAS
Activetoprecharge45(t
RAC
×f
DDR2_CLK
)-15
command
T_RCt
RC
ActivatetoActivate65(t
RC
×f
DDR2_CLK
)-18
commandinthesame
bank
T_RRDt
RRD
ActivatetoActivate10((4×t
RRD
)+(2×t
CK
))/(4×t
CK
)-11
commandinadifferent
bank
T_WTRt
WTR
Writetoreadcommand10(t
WTR
×f
DDR2_CLK
)-11
delay
Note:TheequationgivenabovefortheT_RRDfieldappliesonlyfor8bankDDR2memories.
WheninterfacingtoDDR2memorieswithlessthan8banks,theT_RRDfieldshouldbe
calculatedusingthefollowingequation(t
RRD
×f
DDR2_CLK
)-1.
Table20.SDRAMTimingRegister2(SDTIMR2)Configuration
DDR2Data
RegisterFieldManualDataManualFormula(RegisterRegister
NameParameterNameDescriptionValuefieldmustbe≥)Value
T_XSNRt
XSNR
Exitselfrefreshtoanon-read137.5nS(t
XSNR
×f
DDR2_CLK
)-118
command
T_XSRDt
XSRD
Exitselfrefreshtoaread200(t
CK
cycles)t
XSRD
-1199
command
T_RTPt
RTP
Readtoprechargecommanddelay7.5nS(t
RTP
×f
DDR2_CLK
)-11
T_CKEt
CKE
CKEminimumpulsewidth3(t
CK
cycles)t
CKE
-12
SPRU986B–November2007DDR2MemoryController39
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