Texas Instruments TMS320DM643 Computer Hardware User Manual


 
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3.2.1ConfiguringSDRAMBankConfigurationRegister(SDBCR)
3.2.2ConfiguringSDRAMRefreshControlRegister(SDRCR)
SupportedUseCases
TheSDRAMbankconfigurationregister(SDBCR)containsregisterfieldsthatconfiguretheDDR2
memorycontrollertomatchthedatabuswidth,CASlatency,numberofbanks,andpagesizeofthe
attachedDDR2memory.Inthisexample,weassumethefollowingconfiguration:
Databuswidth=32bits
CASlatency=4
Numberofbanks=8
Pagesize=1024words
Table16showstheresultingSDBCRconfiguration.NotethatthevalueoftheTIMUNLOCKbitis
dependentonwhetherornotitisdesirabletounlockSDTIMRandSDTIMR2.TheTIMUNLOCKbitshould
onlybesetto1whentheSDTIMRandSDTIMR2needstobeupdated.
Table16.SDRAMBankConfigurationRegister(SDBCR)Configuration
FieldValueFunctionSelection
TIMUNLOCKxSetto1tounlocktheSDRAMtimingregister(SDTIMR)andtheSDRAMtimingregister2
(SDTIMR2).Clearedto0tolockSDTIMRandSDTIMR2.
NM0hToconfiguretheDDR2memorycontrollerfora32-bitdatabuswidth.
CL4hToselectaCASlatencyof4.
IBANK3hToselect8internalDDR2banks.
PAGESIZE2hToselect1024-wordpagesize.
TheSDRAMrefreshcontrolregister(SDRCR)configurestheDDR2memorycontrollertomeettherefresh
requirementsoftheattachedDDR2device.SDRCRalsoallowstheDDR2memorycontrollertoenterand
exitselfrefreshandenableanddisabletheMCLKstopping.Inthisexample,weassumethattheDDR2
memorycontrollerisnotisinself-refreshmodeandthatMCLKstoppingisdisabled.
TheRRbitfieldinSDRCRisdefinedastherateatwhichtheattachedDDR2deviceisrefreshedinDDR2
cycles.Thevalueofthisfieldmaybecalculatedusingthefollowingequation:
RR=DDR2clockfrequency×DDR2refreshrate
Table17displaystheDDR2-400refreshratespecification.
Table17.DDR2MemoryRefreshSpecification
SymbolDescriptionValue
t
REF
AveragePeriodicRefreshInterval7.8µs
Therefore,thefollowingassumesa133-MHZDDR2clockfrequency:
RR=133MHZ×7.8µs=1037.4
Therefore,RR=1038=40Eh.
Table18showstheresultingSDRCRconfiguration.
Table18.SDRAMRefreshControlRegister(SDRCR)Configuration
FieldValueFunctionSelection
SR0DDR2memorycontrollerisnotinself-refreshmode.
MCLKSTOPEN0MCLKstoppingisdisabled.
RR40EhSetto40EhDDR2clockcyclestomeettheDDR2memoryrefreshraterequirement.
DDR2MemoryController 38SPRU986BNovember2007
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