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2.4.1RefreshMode
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[12:0]
DDR_BA[2:0]
DDR_DQM[3:0]
RFR
DDR_CLK
PeripheralArchitecture
TheDDR2memorycontrollerissuesrefreshcommandstotheDDR2SDRAMmemory(Figure4).REFR
isautomaticallyprecededbyaDCABcommand,ensuringthedeactivationofallCEspacesandbanks
selected.FollowingtheDCABcommand,theDDR2memorycontrollerbeginsperformingrefreshesata
ratedefinedbytherefreshrate(RR)bitintheSDRAMrefreshcontrolregister(SDRCR).Pageinformation
isalwaysinvalidbeforeandafteraREFRcommand;thus,arefreshcyclealwaysforcesapagemiss.This
typeofrefreshcycleisoftencalledautorefresh.Autorefreshcommandsmaynotbedisabledwithinthe
DDR2memorycontroller.SeeSection2.9formoredetailsonREFRcommandscheduling.
Figure4.RefreshCommand
SPRU986B–November2007DDR2MemoryController13
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