Filter
Top Products
www.ti.com
2.4.3Activation(ACTV)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
DDR_DQM[3:0]
ACTV
DDR_A[12:0]
DDR_CAS
BANK
ROW
DDR_CLK
PeripheralArchitecture
TheDDR2memorycontrollerautomaticallyissuestheactivate(ACTV)commandbeforeareadorwriteto
aclosedrowofmemory.TheACTVcommandopensarowofmemory,allowingfutureaccesses(readsor
writes)withminimumlatency.ThevalueofDDR_BA[2:0]selectsthebankandthevalueofA[12:0]selects
therow.WhentheDDR2memorycontrollerissuesanACTVcommand,adelayoft
RCD
isincurredbefore
areadorwritecommandisissued.Figure7showsanexampleofanACTVcommand.Readsorwritesto
thecurrentlyactiverowandbankofmemorycanachievemuchhigherthroughputthanreadsorwritesto
randomareasbecauseeverytimeanewrowisaccessed,theACTVcommandmustbeissuedanda
delayoft
RCD
incurred.
Figure7.ACTVCommand
DDR2MemoryController 16SPRU986B–November2007
SubmitDocumentationFeedback