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2.13.2InitializingFollowingDevicePowerUpandDeviceRESET
PeripheralArchitecture
CAUTION
Thefollowingpower-upsequenceispreliminaryandisdocumentedto
reflecttheintended-usecase.Thispower-upsequencemaychangeata
futuredate.
Followingdevicepowerup,theDDR2memorycontrollerisheldinresetwiththeinternalclockstothe
modulegatedoff.BeforereleasingtheDDR2memorycontrollerfromreset,theclockstothemodulemust
beturnedon.Performthefollowingstepswhenturningtheclocksonandinitializingthemodule:
1.ProgramPLLC2registerstoprovideastableclockonPLL2_SYSCLK1atthedesiredfrequency.
2.ProgramtheDDR2memorycontrollerPowerandSleepController(PSC)toenableVCLK.
3.FollowtheregisterinitializationproceduredescribedinSection2.13.1tocompletetheDDR2memory
controllerconfiguration.
4.PerformadummyreadofDDR2memorytoverifyinitializationsequencehascompleted.
5.PerformasoftresetoftheDDR2memorycontrollerviathePSCusingthefollowingprocedure.See
theTMS320DM643xDMPDSPSubsystemReferenceGuide(SPRU978)fordetailsonhowto
programthePSC.
a.ToputtheDDR2memorycontrollerintosoftreset,programthePSCtoplacetheDDR2memory
controllerintotheSyncResetstate.
b.TotaketheDDR2memorycontrolleroutofsoftreset,programthePSCtoplacetheDDR2
memorycontrollerintotheEnablestate.
6.EnableVTPmanualcalibrationbywritingtotheVTPIOcontrolregister(VTPIOCR).SeeSection4.12
fordetailsonVTPIOCR.
a.Withasinglewrite,settheENbitfield(bit13)to1andtheRECALbitfield(bit15)to0bywritinga
valueof0000201Fh.
b.SettheRECALbitfield(bit15)to1,makingsurethevaluewrittentotheENfieldisstill1bywriting
avalueof0000A01Fh.Thisbeginsthecalibrationsequence.
7.Waitforaminimumof33VTPclkcyclesforcalibrationtocomplete.TheVTPclockoperatesat
13.5MHZ.
8.EnableaccesstotheDDRVTPregisterbywritinga1totheDDRVTPenableregister.
9.ReadtheDDRVTPregistertogettheP/NchannelVTPvalue.SeeSection4.13fordetailsonthe
DDRVTPregister.
10.WritetheVTPinformationtothePCHandNCHfieldsintheVTPIOCR.MakesuretheRECALandEN
bitsremainsetto1.
11.Write0toENbitfieldintheVTPcontrolregistertodisableVTPcalibration.
12.DisableaccesstotheDDRVTPregisterbywritinga0totheDDRVTPenableregister.
13.DisableVTPinputclockbydisablingthebypassclockofPLL2.
Note:IftheDDR2memorycontrollerisresetviathePowerandSleepController(PSC)andthe
VTPinputclockisdisabled,accessestotheDDR2memorycontrollerwillnotcomplete.To
re-enableaccessestotheDDR2memorycontroller,enabletheVTPinputclockandthen
performtheVTPcalibrationsequenceagain.
SPRU986B–November2007DDR2MemoryController33
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