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2.4.6ModeRegisterSet(MRSandEMRS)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
COL
MRS/EMRS
DDR_A[12:0]
DDR_CAS
BANK
DDR_CLK
PeripheralArchitecture
DDR2SDRAMcontainsmodeandextendedmoderegistersthatconfiguretheDDR2memoryfor
operation.Theseregisterscontrolbursttype,burstlength,CASlatency,DLLenable/disable(onDDR2
device),single-endedstrobe,etc.
TheDDR2memorycontrollerprogramsthemodeandextendedmoderegistersoftheDDR2memoryby
issuingMRSandEMRScommands.WhentheMRSorEMRScommandisexecuted,thevalueon
DDR_BA[1:0]selectsthemoderegistertobewrittenandthedataonDDR_A[12:0]isloadedintothe
register.Figure10showsthetimingforanMRSandEMRScommand.
TheDDR2memorycontrolleronlyissuesMRSandEMRScommandsduringtheDDR2memorycontroller
initializationsequence.SeeSection2.13formoreinformation.
Figure10.DDR2MRSandEMRSCommand
SPRU986B–November2007DDR2MemoryController19
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