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2.16.1DDR2MemoryControllerClockStopProcedure
2.17EmulationConsiderations
PeripheralArchitecture
CAUTION
Thefollowingclockstopproceduresarepreliminaryandaredocumented
toreflecttheintended-usecases.Theseclockstopproceduresmay
changeatafuturedate.
Note:IfanaccessoccurstotheDDR2memorycontrolleraftercompletingsteps1-5,theDLLwill
wakeupandlock,thentheMCLKwillturnonandtheaccesswillbeperformed.Following
step6,allDDR2accessesaredisableduntiltheDDR2memorycontrollerisenabledagain
throughtheLPSC.
ToachievemaximumpowersavingsVCLK,MCLK,X2_CLK,DDR_CLK,andDDR_CLKshouldbegated
off,aswellastheDDR2memorycontrollerDLLpowereddown.Performthefollowingprocedurewhen
shuttingdownclockstoachievemaximumpowersavings:
1.AllowsoftwaretocompletethedesiredDDR2transfers.
2.SettheSRbitintheDDR2SDRAMrefreshcontrolregister(SDRCR).TheDDR2memorycontroller
willcompleteanyoutstandingaccessesandbackloggedrefreshcyclesandthenplacetheexternal
DDR2memoryinself-refreshmode.
3.SettheMCLKSTOPENbitinSDRCR.ThisenablestheDDR2memorycontrollertoshutofftheMCLK.
4.SettheDLLPWRDNbitintheDDRPHYcontrolregister(DDRPHYCR)to1topowerdowntheDDR2
memorycontrollerDLL.
5.PollthePHYRDYbitintheSDRAMstatusregister(SDRSTAT)tobealogic-lowindicatingthatthe
MCLKhasbeenstoppedandtheDLLispowereddown.
6.ProgramDDR2memorycontrollerLPSCtodisableVCLK.
7.ProgramPLLC2registerstostopPLL2_SYSCLK1whichdisablesX2_CLKoftheDDR2memory
controller,aswellasDDR_CLKandDDR_CLK.
Toturnclocksbackon:
1.ProgramPLLC2registerstostartPLL2_SYSCLK1whichsourcesX2_CLKoftheDDR2memory
controller.
2.OncePLL2_SYSCLK1isstable,programtheDDR2memorycontrollerLPSCtoenableVCLK.
3.CleartheMCLKSTOPENbitintheDDR2SDRAMrefreshcontrolregister(SDRCR)to0.
4.CleartheDLLPWRDNbitintheDDRPHYcontrolregister(DDRPHYCR)to0topoweruptheDDR2
memorycontrollerDLL.
5.PerformasoftresetoftheDDR2memorycontrollerviathePSCusingthefollowingprocedure.See
theTMS320DM643xDMPDSPSubsystemReferenceGuide(SPRU978)fordetailsonhowto
programthePSC.
a.ToputtheDDR2memorycontrollerintosoftreset,programthePSCtoplacetheDDR2memory
controllerintotheSyncResetstate.
b.TotaketheDDR2memorycontrolleroutofsoftreset,programthePSCtoplacetheDDR2
memorycontrollerintotheEnablestate.
6.CleartheSRbitinSDRCRto0.
TheDDR2memorycontrollerwillremainfullyfunctionalduringemulationhaltstoallowemulationaccess
toexternalmemory.
SPRU986B–November2007DDR2MemoryController35
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