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Preface...............................................................................................................................6
1Introduction................................................................................................................7
1.1PurposeofthePeripheral.......................................................................................7
1.2Features...........................................................................................................7
1.3FunctionalBlockDiagram.......................................................................................8
1.4SupportedUseCaseStatement...............................................................................8
1.5IndustryStandard(s)ComplianceStatement.................................................................8
2PeripheralArchitecture................................................................................................9
2.1ClockControl.....................................................................................................9
2.2MemoryMap....................................................................................................10
2.3SignalDescriptions.............................................................................................11
2.4ProtocolDescription(s).........................................................................................12
2.5MemoryWidthandByteAlignment..........................................................................20
2.6EndiannessConsiderations...................................................................................21
2.7AddressMapping...............................................................................................22
2.8DDR2MemoryControllerInterface..........................................................................26
2.9RefreshScheduling............................................................................................29
2.10Self-RefreshMode..............................................................................................29
2.11ResetConsiderations..........................................................................................30
2.12VTPIOBufferCalibration.....................................................................................31
2.13Auto-InitializationSequence...................................................................................31
2.14InterruptSupport................................................................................................34
2.15DMAEventSupport............................................................................................34
2.16PowerManagement............................................................................................34
2.17EmulationConsiderations.....................................................................................35
3SupportedUseCases................................................................................................36
3.1ConnectingtheDDR2MemoryControllertoDDR2Memory.............................................36
3.2ConfiguringMemory-MappedRegisterstoMeetDDR2-400Specification.............................36
4DDR2MemoryControllerRegisters.............................................................................40
4.1SDRAMStatusRegister(SDRSTAT)........................................................................41
4.2SDRAMBankConfigurationRegister(SDBCR)............................................................42
4.3SDRAMRefreshControlRegister(SDRCR)................................................................44
4.4SDRAMTimingRegister(SDTIMR)..........................................................................45
4.5SDRAMTimingRegister2(SDTIMR2)......................................................................46
4.6PeripheralBusBurstPriorityRegister(PBBPR)...........................................................47
4.7InterruptRawRegister(IRR)..................................................................................48
4.8InterruptMaskedRegister(IMR).............................................................................49
4.9InterruptMaskSetRegister(IMSR)..........................................................................50
4.10InterruptMaskClearRegister(IMCR).......................................................................51
4.11DDRPHYControlRegister(DDRPHYCR)..................................................................52
4.12VTPIOControlRegister(VTPIOCR)........................................................................53
4.13DDRVTPRegister(DDRVTPR)..............................................................................54
4.14DDRVTPEnableRegister(DDRVTPER)...................................................................54
AppendixARevisionHistory.............................................................................................55
SPRU986B–November2007TableofContents3
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