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2.8DDR2MemoryControllerInterface
Command/Data
Scheduler
Command FIFO
Write FIFO
Read FIFO
Registers
Command
to Memory
Write Data
to Memory
Read Data
from
Memory
Command
Data
PeripheralArchitecture
Tomovedataefficientlyfromon-chipresourcestoexternalDDR2SDRAMmemory,theDDR2memory
controllermakesuseofacommandFIFO,awriteFIFO,areadFIFO,andcommandanddataschedulers.
Table11describesthepurposeofeachFIFO.
Figure14showstheblockdiagramoftheDDR2memorycontrollerFIFOs.Commands,writedata,and
readdataarriveattheDDR2memorycontrollerparalleltoeachother.Thesameperipheralbusisusedto
writeandreaddatafromexternalmemoryaswellasinternalmemory-mappedregisters.
Table11.DDR2MemoryControllerFIFODescription
FIFODescriptionDepth(64-bitdoublewords)
CommandStoresallcommandscomingfromon-chiprequestors7
WriteStoreswritedatacomingfromon-chiprequestorstomemory11
ReadStoresreaddatacomingfrommemorytoon-chiprequestors17
Figure14.DDR2MemoryControllerFIFOBlockDiagram
26DDR2MemoryControllerSPRU986B–November2007
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