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Clock Phase and Polarity Controls
13-4
13.3 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity
using two bits in the SPI control register (SPICON 9A
H
). The clock polarity is
specified by the CPOL control bit, which selects an active high or active low
clock, and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two different transfer for-
mats. The clock phase and polarity should be identical for the master SPI de-
vice and the communicating slave device. In some cases, the phase and polar-
ity are changed between transfers to allow a master device to communicate
with peripheral slaves having different requirements.
When CPHA = 0, the SPI standard defines that the SS
line must be negated
and reasserted between each successive serial byte. This is more difficult
when using the FIFO to transmit the bytes and cannot be done at higher clock
speeds.
When CPHA = 1, the SS
line can remain low between successive transfers.