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16 EPSON S1C88650 TECHNICAL MANUAL
4 INITIAL RESET
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is
to input a LOW level simultaneously to the input
ports (K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for 65536/fOSC1 seconds (two seconds
when the oscillation frequency is fOSC1 = 32.768
kHz) or more to perform the initial reset by means
of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
Multiple key entry reset
■■ Not use
■■ K00 & K01
■■ K00 & K01 & K02
■■ K00 & K01 & K02 & K03
For instance, let's say that mask option "K00 & K01
& K02 & K03" is selected, when the input level at
input ports K00–K03 is simultaneously LOW, initial
reset will take place.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4.1.3 Initial reset sequence
After cancellation of the LOW level input to the
_________
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (512/fOSC3 sec.) have
elapsed.
Figure 4.1.3.1 shows the operating sequence
following initial reset release.
The CPU starts operating in synchronization with
the OSC3 clock after reset status is released.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time, following cancellation of the LOW level
simultaneous input.
(2) Other than during SLEEP status, an initial reset
will be triggered 65536/f
OSC3 seconds after a
LOW level simultaneous input. In this case,
since a reset differential pulse (64/fOSC1
seconds) is generated within the S1C88650, the
CPU will start even if the LOW level
simultaneous input status is not canceled.
Note: The oscillation stabilization time described in
this section does not include oscillation start
time. Therefore the time interval until the
CPU starts executing instructions after
power is turned on or SLEEP status is
cancelled may be longer than that indicated
in the figure below.
PC PC PC 00-0000
Dummy Dummy
VECL
512/f
OSC3
[sec]
Oscillation stable waiting time Dummy cycle Reset exception processing
f
OSC3
Reset signal
Reset release clock
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
∗ Reset status is maintained
during this period.
Internal initial reset release
Reset release
Fig. 4.1.3.1 Initial reset sequence