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Vol. 2A 3-175
INSTRUCTION SET REFERENCE, A-M
CPUID—CPU Identification
Table 3-16. More on Feature Information Returned in the EDX Register
Bit # Mnemonic Description
0 FPU Floating Point Unit On-Chip. The processor contains an x87 FPU.
1 VME Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
including CR4.VME for controlling the feature, CR4.PVI for protected mode
virtual interrupts, software interrupt indirection, expansion of the TSS with
the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
2 DE Debugging Extensions. Support for I/O breakpoints, including CR4.DE for
controlling the feature, and optional trapping of accesses to DR4 and DR5.
3 PSE Page Size Extension. Large pages of size 4 MByte are supported, including
CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page
Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.
4 TSC Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD
for controlling privilege.
5 MSR Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and
WRMSR instructions are supported. Some of the MSRs are implementation
dependent.
6 PAE Physical Address Extension.
Physical addresses greater than 32 bits are
supported: extended page table entry formats, an extra level in the page
translation tables is defined, 2-MByte pages are supported instead of 4
Mbyte pages if PAE bit is 1. The actual number of address bits beyond 32 is
not defined, and is implementation specific.
7 MCE Machine Check Exception. Exception 18 is defined for Machine Checks,
including CR4.MCE for controlling the feature. This feature does not define
the model-specific implementations of machine-check error logging,
reporting, and processor shutdowns. Machine Check exception handlers may
have to depend on processor version to do model specific processing of the
exception, or test for the presence of the Machine Check feature.
8 CX8 CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits)
instruction is supported (implicitly locked and atomic).
9 APIC APIC On-Chip. The processor contains an Advanced Programmable Interrupt
Controller (APIC), responding to memory mapped commands in the physical
address range FFFE0000H to FFFE0FFFH (by default - some processors
permit the APIC to be relocated).
10 Reserved Reserved
11 SEP SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and
associated MSRs are supported.
12 MTRR Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR
contains feature bits that describe what memory types are supported, how
many variable MTRRs are supported, and whether fixed MTRRs are
supported.