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3-180 Vol. 2A CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-M
Example 3-1. Example of Cache and TLB Interpretation
The first member of the family of Pentium 4 processors returns the following informa-
tion about caches and TLBs when the CPUID executes with an input value of 2:
EAX 66 5B 50 01H
EBX 0H
ECX 0H
EDX 00 7A 70 00H
Which means:
• The least-significant byte (byte 0) of register EAX is set to 01H. This indicates
that CPUID needs to be executed once with an input value of 2 to retrieve
complete information about caches and TLBs.
• The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0,
indicating that each register contains valid 1-byte descriptors.
• Bytes 1, 2, and 3 of register EAX indicate that the processor has:
— 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-
MByte pages.
— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.
— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte
cache line size.
• The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.
• Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:
— 00H - NULL descriptor.
— 70H - Trace cache: 12 K-μop, 8-way set associative.
— 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored,
64-byte cache line size.
— 00H - NULL descriptor.
INPUT EAX = 4: Returns Deterministic Cache Parameters for Each Level
When CPUID executes with EAX set to 4 and ECX contains an index value, the
processor returns encoded data that describe a set of deterministic cache parame-
ters (for the cache level associated with the input in ECX). Valid index values start
from 0.
Software can enumerate the deterministic cache parameters for each level of the
cache hierarchy starting with an index value of 0, until the parameters report the
value associated with the cache type field is 0. The architecturally defined fields
reported by deterministic cache parameters are documented in Table 3-12.
The CPUID leaf 4 also reports information about maximum number of cores in a
physical package. This information is constant for all valid index values. Software can