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Vol. 2A 3-669
INSTRUCTION SET REFERENCE, A-M
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String
At the assembly-code level, two forms of this instruction are allowed: the “explicit-
operands” form and the “no-operands” form. The explicit-operands form (specified
with the MOVS mnemonic) allows the source and destination operands to be speci-
fied explicitly. Here, the source and destination operands should be symbols that
indicate the size and location of the source value and the destination, respectively.
This explicit-operands form is provided to allow documentation; however, note that
the documentation provided by this form can be misleading. That is, the source and
destination operand symbols must specify the correct type (size) of the operands
(bytes, words, or doublewords), but they do not have to specify the correct location.
The locations of the source and destination operands are always specified by the
DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the move
string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword
versions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed to
be the source and destination operands, respectively. The size of the source and
destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW
(word move), or MOVSD (doubleword move).
After the move operation, the (E)SI and (E)DI registers are incremented or decre-
mented automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E)SI and (E)DI register are incremented; if the DF flag is 1,
the (E)SI and (E)DI registers are decremented.) The registers are incremented or
decremented by 1 for byte operations, by 2 for word operations, or by 4 for double-
word operations.
The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP
prefix (see “REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix” in
Chapter 4, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B) for block moves of ECX bytes, words, or doublewords.
In 64-bit mode, the instruction’s default address size is 64 bits, 32-bit address size is
supported using the prefix 67H. The 64-bit addresses are specified by RSI and RDI;
32-bit address are specified by ESI and EDI. Use of the REX.W prefix promotes
doubleword operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
DEST ← SRC;
Non-64-bit Mode:
IF (Byte move)
THEN IF DF
= 0
THEN
(E)SI ← (E)SI + 1;
(E)DI ← (E)DI + 1;
ELSE