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Vol. 2A 3-277
INSTRUCTION SET REFERENCE, A-M
DIVSS—Divide Scalar Single-Precision Floating-Point Values
DIVSS—Divide Scalar Single-Precision Floating-Point Values
Description
Divides the low single-precision floating-point value in the destination operand (first
operand) by the low single-precision floating-point value in the source operand
(second operand), and stores the single-precision floating-point result in the destina-
tion operand. The source operand can be an XMM register or a 32-bit memory loca-
tion. The destination operand is an XMM register. The three high-order doublewords
of the destination operand remain unchanged. See Chapter 10 in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of a
scalar single-precision floating-point operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0]← DEST[31:0] / SRC[31:0];
(* DEST[127:32] unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
DIVSS __m128 _mm_div_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
#UD If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 0.
Opcode Instruction 64-Bit
Mode
Compat/
Leg
Mode
Description
F3 0F 5E /r DIVSS xmm1,
xmm2/m32
Valid Valid Divide low single-precision floating-
point value in xmm1 by low single-
precision floating-point value in
xmm2/m32.