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3-428 Vol. 2A FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State
INSTRUCTION SET REFERENCE, A-M
Implementation Note
The order in which the processor signals general-protection (#GP) and page-fault
(#PF) exceptions when they both occur on an instruction boundary is given in Table
5-2 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
3B. This order vary for FXSAVE for different processor implementations.