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3-540 Vol. 2A LFENCE—Load Fence
INSTRUCTION SET REFERENCE, A-M
LFENCE—Load Fence
Description
Performs a serializing operation on all load-from-memory instructions that were
issued prior the LFENCE instruction. This serializing operation guarantees that every
load instruction that precedes in program order the LFENCE instruction is globally
visible before any load instruction that follows the LFENCE instruction is globally
visible. The LFENCE instruction is ordered with respect to load instructions, other
LFENCE instructions, any MFENCE instructions, and any serializing instructions (such
as the CPUID instruction). It is not ordered with respect to store instructions or the
SFENCE instruction.
Weakly ordered memory types can be used to achieve higher processor performance
through such techniques as out-of-order issue and speculative reads. The degree to
which a consumer of data recognizes or knows that the data is weakly ordered varies
among applications and may be unknown to the producer of this data. The LFENCE
instruction provides a performance-efficient way of insuring load ordering between
routines that produce weakly-ordered results and routines that consume that data.
It should be noted that processors are free to speculatively fetch and cache data from
system memory regions that are assigned a memory-type that permits speculative
reads (that is, the WB, WC, and WT memory types). The PREFETCHh instruction is
considered a hint to this speculative behavior. Because this speculative fetching can
occur at any time and is not tied to instruction execution, the LFENCE instruction is
not ordered with respect to PREFETCHh instructions or any other speculative fetching
mechanism (that is, data could be speculative loaded into the cache just before,
during, or after the execution of an LFENCE instruction).
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
Wait_On_Following_Loads_Until(preceding_loads_globally_visible);
Intel C/C++ Compiler Intrinsic Equivalent
void _mm_lfence(void)
Exceptions (All Modes of Operation)
#UD If the LOCK prefix is used.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F AE /5 LFENCE Valid Valid Serializes load operations.